1. Field of the Invention
This disclosure relates to a level shifter having an extended input level, and more particularly, to a level shifter which can operate in response to an input signal of a low level by allowing an output portion and an output control portion to operate in direct response to the input signal.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional level shifter. Referring to FIG. 1, a level shifter 100 in response to input signal IN, having first level or ground level values outputs output signal OUT having a value shifted to a second level or the ground level.
In the operation of the level shifter 100, the first level value is equivalent to a first power voltage Vcc and the second level value is equivalent to a second power voltage Vpp. The level shifter 100 includes a first control transistor P1, a second control transistor N1, a first output transistor P2, a second output transistor N2, and an inverter INV. The first control transistor P1 and the first output transistor P2 are PMOS transistors while the second transistor N1 and the second output transistor N2 are NMOS transistors.
When the input signal IN has the ground level value, the second control transistor N1 is turned off and an inverted input signal INB that is obtained as the input signal IN is inverted is input to a gate of the second output transistor N2. Thus, the second output transistor N2 is turned on in response to the inverted input signal INB and the output signal OUT has the ground level value.
The first control transistor P1 is turned on in response to the output signal OUT having the ground level value and the voltage Vpp of the second level is supplied to a gate of the first output transistor P2. Thus, the first output transistor P2 is turned off in response to the voltage Vpp of the second level.
Next, when the input signal IN has the first level Vcc value, the second control transistor N1 is turned on and the voltage of the ground level is supplied to a gate of the first output transistor P2. Thus, the first output transistor P2 is turned on in response to the ground level voltage so that the output signal OUTPUT has the second level Vpp value.
The second output transistor N2 is turned off in response to the inverted input signal INB. The first control transistor P1 is turned off in response to the output signal OUT having the second level Vpp value. That is, when the input signal IN having the ground level value is input, the second output transistor N2 and the first control transistor P1 are turned on and the level shifter 100 outputs the output signal OUT having the ground level value. Also, when the input signal IN having the first level Vcc value is input, the first output transistor P2 and the second control transistor N1 are turned on and the level shifter 100 outputs the output signal OUT having a value that is shifted to the second level Vpp value.
As described above, when the level shifter 100 outputs the shifted output signal OUT, in either case of the input signal IN having the first level Vcc value or the ground level value, two transistors are turned on.
However, there is a demand for semiconductor integrated circuits consuming less electric power. Accordingly, the voltage level of an input signal is decreased. However, in the conventional level shifter, since the level of the input signal is shifted by the operation of two transistors being turned on, as the voltage level of the input signal decreases, the speed at which the input signal is shifted decreases and eventually the level shifting cannot be performed with respect to an input signal having a voltage level not greater than a predetermined voltage.
When the input level is shifted from the first level Vcc to the ground level in the conventional level shifter 100, the second output transistor N2 is turned on in response to the input signal IN. However, the first output transistor P2 is turned off in response to the operation of the first control transistor P1 that operates in response to the output signal OUT. Thus, both of the first output transistor P2 and the second output transistor N2 are turned on.
Similarly, when the level of the input signal is shifted from the ground level to the first level Vcc, both of the first control transistor P1 and the second control transistor N1 are turned on. That is, in the conventional level shifter 100, since both first output transistor P2 and second output transistor N2, and both first control transistor P1 and second control transistor N1, are turned on at the moment when the level of the input signal IN is shifted, a current path is formed from the second level Vpp to the ground level so that the transistors are deteriorated.